Synchonous Logic

Most of the systems you will work on are synchronous systems. First we need to understand what that means physically. To do that we need to understand how a synchronous system interfaces with any other system that is not synchronous with it. At the most basic level it gets down to deciding if an input signal is in the high or the low state at a clock transition. If the input is changing at the same time as the clock transition, it might register as either, but the worst case is that the circuit ends up in a meta-stable state. This is like a pole balanced on its end. The more perfectly balanced it is and if it is not disturbed, the longer it will stay near that meta-stable state. In theory, this time is indefinite, that is it can be arbitrarily long, but in practice, for every system there is a time where it is very very unlikely. Its one of those design trade-offs, and a good design means shorter times with lower likelyhood of continued meta-stability. Systems the amplify small differences will work better, and when it goes wrong it just shows up like other noise in the channel.

Within a synchronous system, you can have design margins that make sure that logic values are always stable around the clock signals that they are synchronized to. As long as the components are functioning within spec, you won't see meta-stability within a synchronous system, and there are lots of good ways to synchronize their interconnection reliably. Any issues with this just show up like other noise, and good design minimizes and corrects these errors where the rates can be high enough to justify redundant data for correction and detection. This way designers and architects at the systems level can rely on the systems below to provide repeatable responses to given inputs and timing even in the face of high levels of distortion and noise.