In a parallel signal, some number of bits are signaled separately over that number of wires. Of course, these will also change synchronously and not acording to the designed timings. By multiplying the data rate and dividing the number of bits, interconnect systems can transfer more data over fewer wires. In memory busses (*DIMM-N standards for memory modules), the channels are fairly wide, but still much narrower than the multiple 64 bit values of data and address that must be transferred per cycle. At the other extreme, most storage and networking ends up on single bit, completely serialized signals.

Optical trunk lines transfer data at bits rates well beyond the speed of most logic families and must use specialized chips to step it down. The chip will have 8 or 32 parallel lines, still at very high speeds, but manageable for the high speed (parallel) routing logic needed to switch bundled signals between trunks.

At low speeds, the signal transitions can be slow enough to not have to worry about many complex analog considerations, but the higher the speed, the more everything about the design matters. The high energy transitions needed to send high speed data can bounce off the ends of un-terminated traces and blot out the signal. Bottom line, know the standards that matter, and use the right interconnections.